The First IA-64 Microprocessor
Stefan Rusu, Gadi Singer
Intel Corporation
IEEE Journal of Solid-state Circuits
Vol. 35, No. 11
November 2000
pp. 1539-1544
Abstract
The first implementation of the IA-64 architecture achieves high performance by
using a highly parallel execution core, while maintaining binary compatibility with the
IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design
maximizes performance through hardware and software synergy. The processor contains
25.4 million transistors and operates at 800 MHz. The chip is fabricated in a
0.18-um CMOS process with six metal layers and packaged in a 1012-pad organic land grid
array using C4 (flip-chip) assembly technology. A core speed back-side bus connects
the processor to a 4-MB L3 cache.
Index Terms
Clock deskew, design for test, explicitly parallel instruction computing, IA-64, I/O
compensation, microprocessor, source-synchronous bus.
Notes - Interesting use of parity and EDAC along with skew control.
Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal